Open AccessA Comparative Study of Ring Oscillator PUFs Implementation on Different FPGA Families
Author(s) -
Muslim Mustapa,
Mohammed Niamat
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1962/1/012054
Subject(s) - field programmable gate array , ring oscillator , reliability (semiconductor) , physical unclonable function , computer science , aliasing , chip , process variation , process (computing) , embedded system , reliability engineering , voltage , electronic engineering , engineering , electrical engineering , cryptography , algorithm , physics , artificial intelligence , telecommunications , power (physics) , quantum mechanics , undersampling , operating system
Physical Unclonable Function (PUF) is an irreversible function that utilizes the process variation which occurs during silicon chip fabrication. The process variation is uncontrollable; thus, it cannot be modeled and is unique for each chip. Ring Oscillator PUF (ROPUF) has been used in the past to enhance the physical security of FPGAs by generating unique IDs which exploit the process variation introduced during the manufacturing process of the FPGA. In this paper, we describe the implementation and analysis of ROPUF on two different Xilinx FPGA families using 28 nm (Artix-7) and 90 nm (Spartan 3E) technologies. In each case, the ROPUF design is evaluated in terms of five parameters, namely, uniqueness, reliability, uniformity, bit aliasing, and diverseness. The reliability is measured based on responses generated from ROPUF at various temperature and voltage settings. The accelerated aging experiment results are also presented in the reliability evaluation. Our results show that the Artix-7 family yields the best results for uniqueness (45.15%) and diverseness (3.88). Based on the experimental results obtained, we suggest the scheme to increase the ROPUF’s reliability on both Spartan 3E and Artix-7 FPGAs by selecting ROs comparison pairs that have high frequency difference. We showed that the ROPUFs security is not been compromised by applying the scheme.