Open AccessDesign and Simulation of a Small Power Two-Bit MC Circuit via Full Adder Logic
Author(s) -
Soumik Bhattacharjee,
Aparna Vyakaranam,
Devu Satya Svpk,
Sss Shameem,
Rafida Sulo,
Ahmad Anwar Zainuddin
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1962/1/012029
Subject(s) - comparator , adder , computer science , very large scale integration , arithmetic logic unit , logic gate , arithmetic , electronic engineering , transistor , logic synthesis , computer hardware , transistor count , power (physics) , electrical engineering , embedded system , engineering , mathematics , cmos , algorithm , voltage , physics , quantum mechanics
In Very Large-Scale Integration (VLSI) systems, a magnitude comparator (MC) is a component of Arithmetic Logic Unit (ALU) used to make binary decisions. Recent technologies demand the use of power-efficient methodologies as well as techniques that require a lesser number of transistors. In this paper, a magnitude comparator is developed using full adder design logic. Full adders are basic components of the ALU which is the logical and arithmetical unit of the microprocessors and Digital Signal Processing (DSP). This design consumes less power and area when compared to other logic styles in the literature. The proposed comparator has been designed using DSCH 3.5 and simulations are done on Microwind 3.5 via 0.12 μ technologies. This comparator shows a power consumption of 31.746μW using 36 transistors. The proposed design exhibits a full adder logic-based comparator with less power consumption and transistor count as compared to those in recent literature.