Open AccessDesign of Network on Chip (NoC) Computing Node for Mesh Topology using Soft-core NIOS-II Processor
Author(s) -
Udaysingh V. Rane,
R. S. Gad,
Charanarur Panem
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1921/1/012075
Subject(s) - computer science , routing table , scalability , node (physics) , mesh networking , parallel computing , topology (electrical circuits) , network packet , network topology , network on a chip , ring network , computer network , embedded system , routing protocol , engineering , operating system , electrical engineering , structural engineering , wireless
Paper discusses the design of computing node for Mesh topology-based Network on Chip (NoC) platform. The computing node has a capability of processing and routing data over four I/O port switch. Mesh topology is popular due to scalability and its simplest form. The platform is design for (N x N) computing nodes, where each node has soft-core based ‘NIOS-II’ processor. Each computing node has four-way switch East, West, North, South and one local port. The Mesh topology uses static look-up table optimized using proper routing algorithms. The lookup table information is used by Virtual Circuit Interface (VCI) of the switch node to forward the packets using combination of priority based round robin diagonal propagation scheduling algorithm. The design of computing node is generated using – Quartus-II ALTERA software and simulated for functional simulation. Such platforms are popular for data parallelism having applications in Smart sensors.