Open AccessA Comparative Study on minimum skew Clock tree distribution algorithms for high-speed Digital Integrated Circuits
Author(s) -
Dominic Mathew,
S. Sophia,
Kiran Kumar Pasupuleti
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1916/1/012125
Subject(s) - skew , clock skew , computer science , algorithm , latency (audio) , digital clock manager , timing failure , parallel computing , tree (set theory) , mathematics , clock signal , jitter , telecommunications , mathematical analysis
In this paper an extensive analysis on clock tree synthesis algorithms are carried out with conventional cts, Mesh based cts, Meshless Multi-source and flexible H-tree multisource cts with mesh. The algorithms are analysed with industry standard placement benchmarks. Latency, clock power, wirelength, number of buffers, and clock skew are observed. The clock distribution algorithm which provides a single digit least skew is picked, the pros and cons of that algorithm is elaborately discussed.