Research Library

open-access-imgOpen AccessData-Level Parallelism Oriented Memory Access and On-Chip Buffering Mechanisms for a Loop Accelerator
Author(s)
Weikang Zhou,
Xianfeng Li,
Mingtao Chen,
Yan Li
Publication year2021
Publication title
journal of physics
Resource typeJournals
PublisherIOP Publishing
Memory access latency is always a bottleneck for the performance improvement of data-intensive applications. Exploiting the memory access patterns of Data-Level Parallelism(DLP) is a promising way for loop accelerators to reduce the latency significantly. This paper proposes two DLP-oriented data provisioning mechanisms to alleviate memory access latency: 1) DLP-oriented memory access(DoMA) for efficiently utilizes the available memory bandwidth. 2) a data access patterns aware on-chip buffer(PABUF) for exploiting reuse in a user-transparent manner. Unlike those loop accelerators using traditional DMA to access global memory, DoMA efficiently reduces the transmission of useless data by adjusting the size of requests intelligently. In addition, PABUF, which manages data using DLP’s memory access patterns without software engineering efforts, allows the loop accelerators to access data in parallel. Experiments show that when our mechanisms are integrated into a loop accelerator based on Rocket Chip Coprocessor(RoCC), it can achieve 4.20x-10.65x(6.81x on average) speedups with negligible overhead of power and area compared to L1 Cache.
Subject(s)chip , combinatorics , computer architecture , computer science , embedded system , loop (graph theory) , mathematics , parallel computing , parallelism (grammar) , telecommunications
Language(s)English
SCImago Journal Rank0.21
H-Index85
eISSN1742-6596
pISSN1742-6588
DOI10.1088/1742-6596/1914/1/012047

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