Open AccessRealization of Strong CMOS Conforming Full Adder Circuit Using Symmetric Function Lattice Structure
Author(s) -
Muhazam Mustapha,
Bakhtiar Affendi Rosdi,
Tengku Norliza Tengku Mohamad,
Abdul Halim Mokhtar
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1878/1/012027
Subject(s) - adder , transistor , cmos , electronic circuit , computer science , lattice (music) , boolean function , realization (probability) , serial binary adder , arithmetic , electronic engineering , mathematics , topology (electrical circuits) , electrical engineering , voltage , algorithm , physics , engineering , combinatorics , statistics , acoustics
Due to the physical limit that the IC industry may face in the future that transistors size may not be able to shrink anymore,a lot of work had been done to minimize the number of transistors used, instead of shrinking them. One of the highly researched standard circuit to reduce transistor count is the full adder as it appears in almost all computing circuits. In this paper, an alternative to CMOS technology using symmetric Boolean function lattice structure is presented to produce full adder. Symmetric functions are the functions that are invariant under input permutation. Theyhaveaspecialwayofrealizationthat offerssomepossibility to reducethe number oftransistors used. Full adder falls into this classof functions. It has been found that the right full adder lattice structure based circuit only requires 22 transistors to produce the correct function for the sum and c out output. This is a saving of 6 transistors as compared to the standard 28-transistor CMOS full adder. The output delay is around 3.0 ns for the c out output, and around 4.5 ns for the sum output.