Open AccessA Low-bit And Data-conversion-free Memristive Spiking Computing Network
Author(s) -
Guanchao Qiao,
Shaogang Hu
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1828/1/012065
Subject(s) - memristor , crossbar switch , mnist database , computer science , multiplication (music) , artificial neural network , spiking neural network , massively parallel , neuromorphic engineering , data conversion , binary number , bit array , computer hardware , artificial intelligence , parallel computing , electronic engineering , arithmetic , mathematics , engineering , mechanical engineering , telecommunications , drilling , combinatorics
Memristor crossbar holds promising potential in massively parallel data processing, as computing tasks beyond vector-matrix multiplication typically requires additional complex data conversion modules. In this work, we report a memristive spiking computing network (MSCN) without data conversion. Two memristor crossbars are used to perform vector-matrix multiplication, while spiking neurons are used to integrate the signals from each column of the memristor crossbars. Input and output signals are binary spikes (spiking or non-spiking); thus data conversions between the analog and digital domains are avoided. The MSCN is suitable for accelerating artificial neural network (ANN). A multi-layer perception (MLP) consisting of four layers is simulated based on the analog MSCN, and recognition accuracy of 98.55% under the MNIST test set is achieved. However, in the practical memristor, it is challenging to adjust conductance analogously and even challenging to implement multi-bit conductance states. Therefore, the memristor conductance states are further reduced to 3 bits and 1 bit. Encouragingly, recognition accuracies just slightly decrease to 98.36% and 97.96% for 3-bit and 1-bit conductance states, respectively, which is cost-effective considering the hardware reliability improvement.