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Implementation and Optimization of Data Prefetching Algorithm Based on LLVM Compilation System
Author(s) -
Yunda Chai,
Mengyao Chen,
Jianan Li,
Lin Han
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1827/1/012136
Subject(s) - instruction prefetch , computer science , cache , cas latency , parallel computing , dram , compiler , latency (audio) , performance improvement , operating system , embedded system , computer hardware , memory controller , telecommunications , operations management , semiconductor memory , economics
In order to reduce the problem of mismatch between high-performance processors and DRAM speeds, current processors have added a cache structure, but the low cache hit rate also seriously affects the actual performance of the program. Data prefetching technology can alleviate the problems of memory access latency and low hit rate caused by the speed difference between high-performance processors and DRAM. Based on the LLVM open source compiler, this article first implements the data prefetch module on the Shenwei platform. This paper improves the prefetch distance algorithm, proposes a new prefetch scheduling algorithm, introduces a cost model to evaluate the prefetch revenue, and accurately determines the insertion timing of the prefetch instruction to improve the cache hit rate. SPEC2006 performance test results show that after optimization, Shenwei 1621 processor single-core can achieve a maximum performance improvement of 50%, and an average performance improvement of 11%.

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