Open AccessDesign of 32-bit cell-based carry-save combinational multiplier with reduced area and propagation delay
Author(s) -
Shruti Suman,
Ngangbam Phalguni Singh,
R. Selvakumar,
Harshita Saini
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1804/1/012195
Subject(s) - adder , multiplier (economics) , combinational logic , carry (investment) , digital signal processing , computer science , propagation delay , very large scale integration , carry save adder , arithmetic , ripple , computer hardware , serial binary adder , parallel computing , algorithm , logic gate , embedded system , mathematics , engineering , electrical engineering , telecommunications , voltage , computer network , finance , latency (audio) , economics , macroeconomics
In Very Large Scale Integrated (VLSI) and Digital Signal Processing (DSP) applications, a Conventional Combinational Multiplier uses a lot of hardware and propagation delay, and that is one of the main issues. The delay is determined by the ripple carries between the adders. Most techniques used in the combinational multiplier depend on the paper-and-pencil shift-and-add (PPSA) algorithm, which uses ripple carry adder architecture. This paper proposes an architecture called Cell-based Carry-Save Combinational Multiplier (CCCM) that focuses on the propagation delay and area. Each row represents a carry-save adder. The carry outputs are passed to the next row. For validating the proposed architecture, 16x16 multiplication is performed and the overall improvement in the delay is 73.32 % while there is a 3.31 % reduction in the area.