Open AccessDesign and Analysis of Dynamic Comparator Implemented Using Stacking Technique
Author(s) -
Shruti Suman,
P. Hruthik Sai Upendra,
Y. Sai Sree Vishnu
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1804/1/012182
Subject(s) - comparator , cmos , converters , electronic engineering , computer science , power (physics) , power consumption , electronic circuit , stacking , dynamic demand , digital electronics , comparator applications , electrical engineering , engineering , voltage , physics , nuclear magnetic resonance , quantum mechanics
Comparatorsareone of the basic devices that is mostly used in analog-to-digital converters (ADC). Designing low-power circuits with CMOS technology has been a serious research problem for several years. Nowadays the need of low power electronics became vital in various fields. In this paper, stacking technique is used to reduce the power consumed by the comparator.65nm CMOS process is used to design and simulate the comparator. The power consumption ofproposed comparator is compared with thepower consumption of double tail dynamic latch comparator. The proposed approach obtained less power consumption results.