Open AccessPerformance Analysis of 5:2 compressor with 58 transistors
Author(s) -
Kothakonda Durga Bhavani,
R. Sireesha,
K. Raju,
M. Ganesh Kumar,
RatalaKoteswara Naik,
Sanam Nagedram
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1804/1/012162
Subject(s) - gas compressor , multiplier (economics) , transistor count , very large scale integration , cmos , transistor , computer science , electronic engineering , electronic circuit , power (physics) , electrical engineering , engineering , voltage , physics , mechanical engineering , quantum mechanics , economics , macroeconomics
In the present generation of VLSI domain, designing a circuit with less power, area, and delay has become challenge for every designer. In this article we have design and implemented a design for 5:2 compressor which is the vital component in CMOS multiplier circuits. The proposed compressor circuit design requires less transistor count i.e. 58 transistors. The Simulation results of proposed 5:2 compressor has substantially expanded the performance of power delay in contrast to earlier designs.