Open AccessImplementation of Efficient Stopping Criteria for Turbo Decoding
Author(s) -
Ruaha Mahdi,
Ahmed A. Hamad
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1804/1/012015
Subject(s) - computer science , throughput , turbo code , decoding methods , viterbi decoder , turbo , error detection and correction , algorithm , computer hardware , real time computing , wireless , telecommunications , automotive engineering , engineering
The cellular systems with 4th generation, Long Term Evolution (LTE) standard have been transmitted the data at higher rates than the 3G, and 2G systems, in an ever-crowded frequency spectrum. This transmission needs more accuracy, high reliability, and throughput with a low area and power consumption. Therefore, it requires an efficient error control coding. Turbo code is used for LTE system for its good error correction ability at low signal to noise power ratio which can approach Shannon limit performance for large frame lengths. This paper presents a simple and efficient modification that can be applied to all present stopping criterion (SC) to achieve the quality of service mentioned previously. It’s proved that using a trimmed sequence of log-likelihood values (LLR) instead of the full length in the algorithms of stopping the iterative decoding has a significant impact on the utilized silicon area and throughput without a significant sacrifice in performance. It also presents a comparison of designing the Soft-Output Viterbi (SOVA) decoder using different arbitrary-precision fixed data types that offers by Vivado high-level synthesis (HLS) instead of the costlier float representation to reduce processing time and consumed area. Due to its high flexibility in designing and implementing prototype systems, the FPGA device (Kintex-7, Xilinx part number XC7K325T-2FFG900C) was utilized with different parallelism and loop pipelining directives to ensure acquiring the targeted initiation interval and silicon area.