Open AccessThe power-delay product and its implication to CMOS Inverter
Author(s) -
Zitong Han
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1754/1/012131
Subject(s) - inverter , pmos logic , nmos logic , cmos , propagation delay , power–delay product , transistor , electronic engineering , electrical engineering , dissipation , power (physics) , computer science , engineering , voltage , physics , adder , quantum mechanics , thermodynamics
Due to power dissipation has always been a significant standard for low power VLSI design, as a parameter that could reflect both circuit power consumption and delay, Power-Delay Product is of great research value. This paper mainly explores the working principle of CMOS inverter, and the definition, and formation causes of PDP. Two experiments were designed based on LTspice for investigating the effect of width to length ratio of the channel of transistors and the stack approach on the propagation delay and dynamic dissipation of CMOS inverter. It is verified that the propagation delay of the inverter is just related to the ratio of the width of the channel between NMOS and PMOS transistors. It is also verified that the range of ratios of the width of the channel between two transistors which makes the propagation delay and PDP minimum is 2∼4, and the stack approach could reduce the PDP in the CMOS inverter effectively.