Open AccessA 2.7GHz sub-sampling phase-locked loop circuit
Author(s) -
Xiaoning Xin,
Peng Xu,
Jinchang Ren,
Wenhu Qiao
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1748/5/052019
Subject(s) - phase locked loop , nmos logic , phase noise , pmos logic , loop (graph theory) , frequency synthesizer , voltage controlled oscillator , phase detector , noise (video) , charge pump , sampling (signal processing) , pll multibit , phase frequency detector , delay locked loop , electronic engineering , physics , cmos , voltage , electrical engineering , engineering , detector , computer science , transistor , capacitor , mathematics , combinatorics , artificial intelligence , image (mathematics)
A 2.7GHz low phase noise sub-sampling phase locked loop is introduced. The low noise performance is realized by using the sampling loop and the frequency lock loop. In the locked state, only the sampling loop works, while the frequency lock loop does not work, and the frequency divider does not work. Therefore, in-band noise generated by the phase detector and charge pump will not be amplified N 2 , so the sampling loop’s in-band noise will be greatly reduced. In order to reduce out-of-band noise, the voltage controlled oscillator is a LCVCO with nmos-pmos complementary structure. The PLL is based on TSMC 130 nm CMOS process. Under the working voltage of 1.8V, PLL consumes 24.6mw.