Open AccessSoftware and hardware co-simulation verification platform for navigation SoC
Author(s) -
Dan Qi,
Mo Chen,
Shaozhen Zhang,
Daizhan Cheng,
Jun Mu
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1735/1/012010
Subject(s) - debugging , computer science , compiler , embedded system , software , verilog , system on a chip , co simulation , computer hardware , hardware description language , computer architecture , software verification , field programmable gate array , software development , operating system , software construction
This paper proposes a software and hardware co-simulation verification platform suitable for satellite navigation SoC chips. The specific implementation scheme is described, and the final simulation results are given. Software simulation is written in c and assembly language, using a complete software compilation and debugging tool chain, hardware simulation is built based on verification methodology, SoC design code is written by verilog, and the software and hardware are coordinated through the VCS compiler to achieve information interaction, and then a universal simulation platform with fast speed, high authenticity and convenient debugging is realized. The simulation results show that the navigation SoC chip functions correctly.