Open AccessDesign of 9:2 compressor using FinFET
Author(s) -
Jyotsna Kolluru,
Teja Viswanadhapalli,
A. Annis Fathima
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1716/1/012045
Subject(s) - gas compressor , electronic circuit , cmos , multiplier (economics) , electronic engineering , computer science , cadence , transistor , digital electronics , power consumption , electrical engineering , power (physics) , engineering , voltage , physics , mechanical engineering , quantum mechanics , economics , macroeconomics
Multiplier is an essential component that is used commonly in any digital circuits. In general, for any digital circuits, multipliers occupy larger area; have long latency and their power consumption is more. Thereby, enhancing the performance of multipliers is quite important. Compressors are used to reduce the partial products so that the improved performance of multipliers can be achieved. In this paper, a new structure of 9:2 compressor is proposed in which the circuit is implemented with different combinations of 3:2, 4:2, 5:2 and 6:2 compressors. In this work, instead of bulk CMOS technology, circuits are implemented using FINFETs as they provide better gate control property, lower short channel effects. All the compressor circuits have been implemented using Cadence Virtuoso Simulator with FINFET 32nm technology. All the circuits are implemented to analyze the performance in terms of power, delay and transistor count.