Open AccessDesign of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic
Author(s) -
Sushil Kumar,
A. Anita Angeline
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1716/1/012034
Subject(s) - domino logic , pass transistor logic , dynamic logic (digital electronics) , logic optimization , logic family , computer science , sequential logic , arithmetic , logic gate , and or invert , logic synthesis , electronic engineering , digital electronics , algorithm , mathematics , electronic circuit , electrical engineering , engineering , transistor , voltage
Design of combinational circuits using dynamic logic has the advantage of high speed and less area when compared to conventional CMOS logic. However, it pose problem while cascading dynamic logic architectures and also more prone to leakage current issue. These issues are overcome by using domino logic with static inverter at the output of dynamic node. The increased power dissipation at the output node is reduced by using pseudo dynamic buffer based domino logic by having static like switching at the output node. This paper details the design of arithmetic and logic unit designed using conventional and pseudo dynamic buffer based domino logic. The arithmetic unit comprise adder, subtractor, multiplier and logical unit comprise AND, NAND, OR, NOR and XOR logic blocks based on pseudo dynamic buffer based domino logic and it is compared with the Arithmetic logic unit designed using conventional domino logic. The design and simulations are performed using UMC90nm technology node library using Cadence ® Virtuoso ® tool. The simulation result of ALU unit demonstrates that arithmetic logic unit designed using PDB logic has reduction in power consumption by 89.14% and delay by 1.995% while compared to conventional domino logic.