Open AccessStudy on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits
Author(s) -
P. Divya Sree,
Balwinder Raj,
B. Srinivas
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1714/1/012043
Subject(s) - comparator , successive approximation adc , interleaving , computer science , electronic engineering , electronic circuit , amplifier , power (physics) , noise (video) , electrical engineering , voltage , engineering , cmos , physics , artificial intelligence , quantum mechanics , image (mathematics)
Comparators play an important role in designing of SAR ADC. In this paper we achieve the required performance of SAR ADC at minimum power usage. Using of comparators will reduce the power and noise, Dynamic latch circuit used in comparator increases the speed. The differential amplifier is also discussed. Here we will get to know about Ramp ADC and also about various DAC’s like M-DAC and AUX-DAC. The time-interleaving technique is the design technique that is used to increase the speed.