Open AccessA Comparison of Single-Buffer and Double-Buffer Design in a Systolic Array Generator
Author(s) -
Dongchu Su,
Li Yong
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1693/1/012197
Subject(s) - buffer (optical fiber) , throughput , computer science , overhead (engineering) , systolic array , field programmable gate array , generator (circuit theory) , circular buffer , computer hardware , convolution (computer science) , power (physics) , embedded system , very large scale integration , wireless , artificial intelligence , physics , telecommunications , quantum mechanics , artificial neural network , programming language , operating system
In application fields such as face recognition and image recognition using deep learning, more convolution operations are required for the increasing amount of data. Therefore, the use of systolic array acceleration is becoming a key technology trend to accelerate the development of deep learning applications. In previous designs, most of the systolic array used single-buffer or double-buffer structures, but most of them did not compare the difference between the two in detail. This work designs and implements a three-level systolic array generator, which can be configured in single-buffer or double-buffer modes. We also program the generated systolic array accelerator on Nexys-Vedio FPGA to explore the performance and overhead of single-buffer and double-buffer structure modes. The results show that the throughput of the double-buffer structure is increased by nearly 3 × compared to the single-buffer structure while only brings an additional 28% power consumption and 25% area overhead under the SIMC 130nm technology. And compared with the previous work, the proposed systolic array generator reduces power consumption by 75% and area overhead by 34% with almost no loss in performance.