Open AccessDesign of a dual-issue RISC-V processor
Author(s) -
Hongsheng Zhang,
Zekun Jiang,
Yong Li
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1693/1/012192
Subject(s) - pipeline (software) , computer science , reduced instruction set computing , processor design , instruction set , dual (grammatical number) , processor register , microarchitecture , application specific instruction set processor , computer architecture , division (mathematics) , pipeline burst cache , media processor , set (abstract data type) , embedded system , computer hardware , parallel computing , operating system , digital signal processor , memory address , arithmetic , digital signal processing , programming language , semiconductor memory , art , mathematics , cache , literature , cpu cache , cache coloring
A dual-issue 32-bit RISC-V processor is designed and reported. In order to evaluate the performance of the dual-issue processor, a single-issue processor based on the open source RISC-V instruction set architecture is first designed for reference and it is also the base of the dual-issue processor. The single-issue reference processor, which has a 5-stage pipeline, supports base integer instruction set, integer multiplication and division and compressed instructions, has passed the corresponding functional and compliance tests. The dual-issue processor extends the pipeline to dual-issue and introduces additional processing to solve data hazards in the pipeline. The evaluated result of the dual-issue processor shows that it has significant performance improvement than the single-issue processor.