Open AccessOptimized Design of FIR Filter Based On FPGA
Author(s) -
Qihui Fu,
Guoqin Zhang,
Xiushan Wu,
Shubin Yan
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1626/1/012143
Subject(s) - adder , field programmable gate array , finite impulse response , filter (signal processing) , multiplication (music) , computer science , algorithm , arithmetic , computer hardware , mathematics , telecommunications , computer vision , combinatorics , latency (audio)
Based on the field programmable gate arrays (FPGA), a low area and high speed FIR filter is proposed and designed. The multiplication modules were replaced by adders and shift registers in the proposed architecture. This is possible because a coefficient approximation is performed, using the algorithm that computes the coefficients like a sum-of-powers-of-two (SOPOT). Compared with the traditional method, the area of the 7-tap 12 bit FIR filter occupied is 75%smaller.