Open AccessDesign of High-Speed Quaternary D Flip-Flop Based on Multiple-valued Current-mode
Author(s) -
Haijun Wu,
Yilong Bai,
Xiaoran Li,
Yiming Wang
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1626/1/012067
Subject(s) - flip flop , very large scale integration , modularity (biology) , computer science , cmos , electronic engineering , sequential logic , propagation delay , logic gate , arithmetic , algorithm , embedded system , engineering , mathematics , biology , genetics
A new type of quaternary D flip-flop based on multiple-valued current-mode is presented for high-speed sequential circuit in VLSI systems. It employs master-slave mode and dynamic multiple-valued source-coupled logic. A distinguishable multiple-valued interval, fast switch speed and compact structure are obtained by combining source-coupled logic with differential-pair circuit. The performance evaluation is carried out with HSPICE using 0.18μm CMOS process. A performance comparison with those issued in some references is conducted. The delay in our design is about 74% reduced by comparison with the corresponding binary implementation. The circuitry proposed is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential and feasible method of high-performance VLSI systems.