Open AccessLow-Latency Ultra-Wideband High-Speed Transmission Protocol Based on FPGA
Author(s) -
Hu Jin-xian,
Jinfeng Wang,
Rengang Li
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1621/1/012066
Subject(s) - computer science , field programmable gate array , data transmission , latency (audio) , computer hardware , transmission (telecommunications) , embedded system , serial communication , low latency (capital markets) , computer network , telecommunications
Aiming at the shortcomings of current high-speed serial transmission protocol including high latency and low effective transmission bandwidth, this paper designs a low-latency, ultra-wideband high-speed serial transmission protocol based on FPGA. Based on homologous system clock, data scrambling and synchronous frame synthesis are used to complete the data integration, so as to increase the effective bandwidth of data transmission. The receiving end reduces the data transmission latency by using the internal logic of FPGA and the buffer pool built by the register group together with status machine. The protocol is simple and universal, which can be applied to the FPGA platform of any OEM. Experiments show that the protocol can effectively reduce data transmission latency, improve the effective bandwidth of data transmission, and monitor the health and error code status of each data transmission channel in real time.