Open AccessFPGA Accelerator Design for License Plate Recognition Based on 1BIT Convolutional Neural Network
Author(s) -
Yulu Cai,
Xiunan Lin,
Hui Qian,
Pei-Min Lu
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1621/1/012022
Subject(s) - field programmable gate array , convolutional neural network , computer science , convolution (computer science) , artificial neural network , artificial intelligence , pattern recognition (psychology) , hardware acceleration , feature (linguistics) , computer hardware , linguistics , philosophy
Aiming at the problem that convolutional neural network is difficult to deploy on small embedded devices due to its high complexity and large storage space requirement, this paper propose a convolutional neural network FPGA accelerator architecture based on binarization. Using the gray scale processing, binarization processing, threshold setting to reduce the number of parameters. Designing Parallel structures of convolution kernels, feature maps, and matrix blocks to accelerate. The designed architecture can be deployed on the AX7103 FPGA development platform with limited resources. The experimental results show that the convolutional neural network after parallel acceleration design can achieve a recognition accuracy rate of 98.73% on the premise of reducing the data bit width from 32 bits to 8 bits, the recognition speed is about 0.21 seconds/time.