Open AccessFailure Analysis of a Chip Damaged by Electro-Static Discharge
Author(s) -
Yaoqing Cheng,
Wei Huang,
Hang Li,
Qian Lingli,
Wei Zhang
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1617/1/012029
Subject(s) - chip , reliability (semiconductor) , electrostatic discharge , reliability engineering , root cause , root cause analysis , computer science , electronic engineering , voltage , engineering , electrical engineering , power (physics) , telecommunications , physics , quantum mechanics
A process of failure analysis of a COMS chip damaged by Electro-Static Discharge (ESD) is presented. The method of the thermal image was used to locate the failure spot. To find out the root of the failure, the circuit principle and the layout of the chip were analyzed, and it was found that the layout design was not unreasonable. An ESD test was carried out to confirm the analysis. This work has reference significance for the failure analysis and reliability improvement of the integrated circuit product.