Open AccessDesign and error-rate evaluation of RSFQ logic gates comprising a toggle storage loop
Author(s) -
Koki Yamazaki,
Hiroshi Shimada,
Yoshinao Mizugaki
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1590/1/012042
Subject(s) - nand gate , logic gate , voltage , loop (graph theory) , rapid single flux quantum , digital electronics , computer science , process (computing) , nor gate , electronic circuit , electronic engineering , electrical engineering , computer hardware , physics , mathematics , engineering , algorithm , quantum mechanics , josephson effect , superconductivity , combinatorics , operating system
We propose an RSFQ digital cell with a toggle storage loop structure for logical NOT operation. Logical NOT operation is a fundamental function of digital circuitry, and hence, it had better be realized with less devices. We demonstrate a simpler and area-halved NOT gate designed as a 40 x 80 μm 2 cell, which follows to cell-based design methodology. Test circuits were fabricated using a 2.5kA/cm 2 Nb integration process. Measurements were executed in a liquid helium bath. We confirmed that the NOT gate comprising a toggle storage loop worked correctly. The error-rate of the NOT gate was less than 8.33 x 10 −6 in the bias voltage range from 2.111 to 3.165 mV, which corresponded to the bias margin from 84.4% to 126.6% of the nominal bias voltage (2.5 mV). We also present that NOR and NAND logic gates can be configured using a toggle storage loop.