Open AccessDesign of 1Gsps high-speed data acquisition card
Author(s) -
Xiunan Sun,
Ming Liu,
H. Liang
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1550/3/032157
Subject(s) - data acquisition , computer hardware , field programmable gate array , computer science , effective number of bits , interface (matter) , ethernet , embedded system , engineering , electronic engineering , operating system , cmos , bubble , maximum bubble pressure method
In order to digitize the High-Frequency signal, a 12-bit 1Gsps RF Sampling data acquisition system is designed. The digital acquisition system includes an Analog-to-Digital Converter (ADC) daughter card and a data processing mother card equipped with Field Programmable Gate Arrays (FPGA) for communication, which has an external DDR3 memory module and a Gigabit Ethernet Interface. It focuses on the hardware system implementation of the daughter card and the realization of data receiving, transferring, and sending based on the FPGA. The test results show that the Effective Number of Bit (ENOB) of the acquisition card is above 9.1 Bits. Both Integral Non-Linear (INL) and Differential Non-Linearity (DNL) are anticipated. It accomplishes the requirements for engineering applications in many fields excellently.