Open AccessDesign of a Dynamic Reconfigurable Microsystem Based on SIP
Author(s) -
Hao Lv,
Zhang Shengbing,
Wei Han,
Yongqiang Liu,
Shuo Liu,
Lei Zhang,
Shiyu Wang
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1549/5/052032
Subject(s) - embedded system , computer science , control reconfiguration , field programmable gate array , system on a chip , flexibility (engineering) , avionics , encryption , logic synthesis , computer architecture , computer hardware , engineering , logic gate , algorithm , computer network , statistics , mathematics , aerospace engineering
In recent years, with the development of microelectronics technology, microsystems based on SIP/SoC have been applied to drone and other avionics systems. It is practical to study the reconfigurable calculation of avionics microsystems facing the flexible use of the scene. Encryption/decryption data based on FPGA can adapt to different application environments and functional requirements, which is especially important for product protection. However, implementing multiple algorithms on the same chip leads to increased logic resource consumption, low resource utilization, and poor system flexibility. In view of the above problems, it is necessary to design a dynamic reconfigurable computing platform based on an aviation SIP micro-system chip with dynamic reconfigurable technology as the core (using Zynq SoC). The platform use on-chip ARM processor to control reconfiguration. The different encryption and decryption algorithm logics are configured into different logical partitions on the chip according to the requirement. The logic circuit is updated and the algorithm is reconstructed. Different encryption and decryption algorithms are implemented by using the HLS method. The verification results show that the design can complete the algorithm switching at a higher configuration speed while the other functions on the chip work normally. Under the premise of ensuring the stability of the system, the on-chip logic resource consumption is reduced, and the resource utilization and system flexibility are improved.