Open AccessCoverage measurement and analysis during verification of DUT
Author(s) -
Armen Boiadzhian,
Zbigniew Lisik,
Irina Hahanova
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1534/1/012012
Subject(s) - computer science , a priori and a posteriori , programming language , model checking , functional verification , reliability engineering , verification , formal verification , computer engineering , software , engineering , software system , software construction , philosophy , epistemology
Verification involves checking the compliance of the system with the requirements of its specification at each level of detail. Given a certain complexity inherent in real systems, formal methods are not applicable for such a resister-transistor level (RTL)-description check, since they are associated with extremely high computational complexity. In practice, in this case, the device’s RTL code is checked by applying test stimulus to the RTL model and controlling the response to either the specification or the reference model. The applied techniques for writing and generating tests do not have a priori guarantees covering all possible situations that allow us to identify bugs in design.