Open AccessResearch on high robustness 4.5kV FRD chip
Author(s) -
Jiang Liu,
Feng He,
Yueyang Liu,
Rui Jin,
Shaohua Dong,
Mingchao Gao
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1486/4/042017
Subject(s) - robustness (evolution) , terminal (telecommunication) , chip , electric field , voltage , materials science , reliability (semiconductor) , optoelectronics , electrical engineering , computer science , engineering , physics , chemistry , telecommunications , biochemistry , power (physics) , quantum mechanics , gene
A robustness 4500V/100A FRD with was designed by simulation and verified by experiment. The chip composed with optimized carrier density cell area and ruggedness terminal area. The cell area composed of P-body/N-sub/N+ layers, has good static and dynamic trade off characteristics by carefully design. The simulation show that there was no difference between conventional multi-deep P-ring terminal and multi-deep P-ring plus inner field plate terminal. Both terminals have the same width and almost the same breakdown voltage, low electric field and etc.by simulation.The experiment show that different terminal chips have almost the same trade off characters but different in reliability test, the inner field plate terminal pass 1000H HTRB test while the conventional multi-deep P-ring terminal failed at 168H HTRB test.