Open AccessSimulation and experiment of a new DC fault current limiter topology
Author(s) -
Wenjie Wang,
Jianzheng Liu
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1449/1/012094
Subject(s) - fault current limiter , current limiting , snubber , limiter , topology (electrical circuits) , voltage , overcurrent , impulse (physics) , current (fluid) , electrical engineering , overvoltage , computer science , electronic engineering , power (physics) , engineering , electric power system , capacitor , physics , quantum mechanics
With the development of high voltage direct current (HVDC) power transmission system, it is imperative to develop a practical current limiting device which can effectively protect the converter from the influence of fault current. Based on the topology of current limiter proposed in previous papers, considering the requirements of practical application conditions, an optimized topology is proposed, which consists of snubber circuit and arrester, both in simulation and experiment. In addition, the RC buffering circuit is added and the parameters are optimized to reduce the voltage impulse that the IGBT of fault current limiter would else bear. Simulation and experiment are carried out in DC system. Both simulation and experiment results can prove the effectiveness of the optimized current limiter circuit.