Open AccessFPGA oriented design method of Adjustable Arbiter Physical Unclonable circuit
Author(s) -
Jiang Zhou
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1449/1/012060
Subject(s) - arbiter , field programmable gate array , computer science , physical unclonable function , embedded system , computer hardware , electronic engineering , engineering
In this paper, the design principle of the Arbiter Physical Unclonable Function (APUF) based on the arbiter is studied, the existing problems are analyzed, and the problem of its delay asymmetry is studied. An adjustable APUF structure for FPGA platform is proposed, which includes three modules. To adjust the delay deviation of the two paths of traditional Apuf flexibly, it is implemented and verified on the actual FPGA, which proves its feasibility and superiority.