Open AccessA Fast-transient NMOS Capacitor-less LDO with Spike Voltage Sampling Amplifier and Transient Enhancement
Author(s) -
Yun Li,
Shanzhou Huang,
Quanzhen Duan
Publication year - 2020
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1449/1/012034
Subject(s) - nmos logic , transient (computer programming) , slew rate , dropout voltage , amplifier , capacitor , voltage , voltage spike , electrical engineering , materials science , transient response , cmos , transistor , control theory (sociology) , engineering , voltage reference , computer science , control (management) , artificial intelligence , operating system
A fully-integrated NMOS low dropout voltage (LDO) with spike voltage sampling amplifier is proposed in this paper to provide a stable power supply for many portable devices and artificial intelligence systems. The proposed Spike Voltage Sampling Amplifier circuit is composed of an error amplifier based on dynamic bias of output voltage and a capacitive coupling network, which is embedded in the circuit to detect fluctuations in the output voltage to increase the slew rate of the power transistor so that it turns on and off quickly. The LDO is implemented in 0.18 um CMOS process, which consumes 84uA quiescent current. It regulates output at 1.6V, with dropout voltage of 200 mV. For load current transients from light load 100 uA to heavy load 20 mA at the 100 ns edge-time, the undershoot of the LDO is 82 mV and the recovery time is 167 ns. Similarly, the load current transient from heavy load to light load produces an overshoot of 67 mV and recovery time is 156 ns.