Open AccessClock Network Synthesis Based on Clock Mesh Technology
Author(s) -
Tao Yi,
YuJing Li,
Yaming Wu
Publication year - 2019
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1345/4/042095
Subject(s) - synchronous circuit , digital clock manager , clock network , computer science , clock gating , clock domain crossing , clock signal , cpu multiplier , asynchronous circuit , embedded system , telecommunications , jitter
Circuit Synthesis plays a very important role among all the digital integrated circuit backend design flow. For the purpose of reducing the clocks latence in the design flow, based on the traditional clock network synthesis method, this paper demonstrates a clock synthesis method, which based on clock mesh technology using IC Complier tool.