Open AccessASIC implementation of Up-sampling Built in 6GS/s-16bit DAC
Author(s) -
Zehua Zhu,
Haiyang Quan,
Zongmin Wang,
Tieliang Zhang,
Xinmang Peng
Publication year - 2019
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1345/2/022015
Subject(s) - interpolation (computer graphics) , application specific integrated circuit , sampling (signal processing) , computer science , digital filter , interface (matter) , electronic engineering , filter (signal processing) , signal (programming language) , computer hardware , engineering , telecommunications , parallel computing , computer vision , bubble , frame (networking) , maximum bubble pressure method , programming language
This paper presents an interpolation filtering model including four Digital interpolation filters. The interpolation filter circuit can effectively increase the data rate without increasing the input rate of the interface, and realize the up-sampling processing of the external input low-frequency digital signal to meet the high-speed DAC core conversion data requirement.