Open AccessThe Research on SAR ADC Integrated Circuit
Author(s) -
Huailiang Li,
Jing Hu
Publication year - 2019
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1314/1/012022
Subject(s) - successive approximation adc , modelsim , computer science , comparator , software , electronic engineering , circuit design , mixed signal integrated circuit , key (lock) , electronic circuit simulation , electronic circuit , computer hardware , integrated circuit , electrical engineering , embedded system , field programmable gate array , engineering , vhdl , voltage , computer security , programming language , operating system
Successive approximation ADCs are widely used in low- and medium-speed applications due to their simpler structure, fewer analog blocks, smaller area, and lower power consumption. The successive approximation ADC mainly includes a sample and hold circuit, a DAC, a comparator, a clock circuit, and a SAR register. The rationality is verified by analyzing, designing and simulating each component circuit. For the research of ADC architecture, SAR type is selected and the key circuit is optimized. Using Cadence layout research, the digital part of ADC circuit can be simulated by Quartus II software and Modelsim software, and the hybrid circuit part is simulated by Candance software PSpice A/D. About layout design, some circuits can be further verified with Proteus software.