Open AccessA Novel Square Root Algorithm and its FPGA Simulation
Author(s) -
Zhou Zhong-cheng,
Jingchun Hu
Publication year - 2019
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1314/1/012008
Subject(s) - square root , algorithm , field programmable gate array , computer science , verilog , root (linguistics) , square (algebra) , normalization (sociology) , mean squared error , mathematics , computer hardware , statistics , linguistics , philosophy , geometry , sociology , anthropology
As a basic operation in elementary mathematics, square root operation is widely used in numerical calculation and digital signal processing. The square root operation is a nonlinear operation and cannot be solved directly on FPGA. Many previous square root algorithms have been proposed. This paper introduces several previous square root algorithms, then presents a novel square root algorithm which uses 16-bit integer input and 16-bit integer output. Using the idea of normalization, the square number is mapped to the range of 0-1, and the square root is approximated by the sum of numerical sequence. We discuss the proposed square root algorithm, error analysis. The proposed algorithm was programmed by the Verilog in Xilinx’s Vivado 17.2 software environment, and the simulation was verified on the Virtex-7 series chip. Compared with other square root algorithms, the algorithm only uses shifter, adders and sub-tractor. It does not involve complex operations, consumes less resources, and it’s suitable for implementation on FPGA.