Open AccessHigh Voltage Intelligent Power Module Layout Design for Parasitic Inductance Reduction
Author(s) -
Hua Qiu,
Jiaxing Zheng,
Shixin Wang,
Zhijian Pan,
Yan Leng,
Jie Sun,
Junfeng Ren
Publication year - 2019
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1237/4/042075
Subject(s) - inductance , design layout record , power (physics) , page layout , power module , parasitic element , computer science , reduction (mathematics) , electronic engineering , electrical engineering , voltage , engineering , circuit extraction , equivalent circuit , physics , geometry , mathematics , quantum mechanics , advertising , business
When designing the high voltage intelligent power module, layout design is as important as circuit design. Appropriate layout design can avoid many problems associated with these types of power modules. This paper relates generally to the layout design of the power stage components within a 600V/30A high voltage SiC intelligent power module for low inductance. Several crucial aspects when designing the power stage layout have been pointed out. It also presents how to optimize the layout design to minimize the parasitic inductance.