Open AccessA survey on multipliers, adders and adiabatic logic styles suitable for power reduction
Author(s) -
S Jagadeesh Babu,
R. Sivakumar
Publication year - 2018
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1026/1/012008
Subject(s) - adder , adiabatic circuit , adiabatic process , multiplier (economics) , electronic engineering , power (physics) , logic gate , electronic circuit , computer science , reduction (mathematics) , power consumption , logic synthesis , arithmetic , logic family , mathematics , electrical engineering , engineering , physics , cmos , geometry , thermodynamics , macroeconomics , quantum mechanics , economics