Open Access
Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel
Author(s) -
Klaas Strempel,
Friedhard Römer,
Yuqing Feng,
Matteo Meneghini,
A. Bakin,
H.H. Wehmann,
Bernd Witzigmann,
A. Waag
Publication year - 2020
Publication title -
semiconductor science and technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.712
H-Index - 112
eISSN - 1361-6641
pISSN - 0268-1242
DOI - 10.1088/1361-6641/abc5ff
Subject(s) - materials science , optoelectronics , gallium nitride , doping , reactive ion etching , etching (microfabrication) , transistor , gate dielectric , dielectric , voltage , nanotechnology , layer (electronics) , electrical engineering , engineering
This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p -doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn -doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p -doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current–voltage and capacitance–voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 × 10 12 cm −2 related to the Al 2 O 3 gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.