The demonstration of a D-SMT stressor on Ge planer n-MOSFETs | Zendy

M.-H. Liao | Zendy; P.-G. Chen | Zendy

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The demonstration of a D-SMT stressor on Ge planer n-MOSFETs

Author(s) -

M.-H. Liao,

P.-G. Chen

Publication year - 2015

Publication title -

aip advances

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.421

H-Index - 58

ISSN - 2158-3226

DOI - 10.1063/1.4919624

Subject(s) - materials science , dislocation , stress (linguistics) , crystal (programming language) , transistor , mosfet , optoelectronics , field effect transistor , electron mobility , germanium , semiconductor , condensed matter physics , electrical engineering , silicon , composite material , computer science , physics , engineering , voltage , philosophy , linguistics , programming language

An approximately 31% Id,sat improvement and 42% mobility enhancement are achieved on the planer Ge n-Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) by implementing the dislocation-stress memorization technology (D-SMT) stressor for the first time, based on an investigation of crystal re-growth velocities along different directions and the optimization of the dislocation angle (θ) in Ge. Ultra-high stress (>3 GPa) capping SiN film is found to be essential for modifying the crystal re-growth velocities along the [100] and [110] directions to optimize the θ. The change of crystal re-growth velocities and the mobility enhancement ratio with the stress along the assigned directions in Ge is also discussed, respectively

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