Open AccessDesign of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test
Author(s) -
Kommey Benjamin,
Boateng Kwame Osei,
Yankey Jephthah,
Addo Ernest Ofosu,
Agbemenu Andrew Selasi,
Tchao Eric Tutu,
Akowuah Bright Yeboah
Publication year - 2023
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/tje2.12211
Subject(s) - phase locked loop , frequency synthesizer , phase noise , dbc , pll multibit , ring oscillator , direct digital synthesizer , electronic engineering , chip , fault (geology) , computer science , voltage controlled oscillator , electrical engineering , engineering , voltage , seismology , geology
This paper presents the design of an on‐chip charge pump phase‐locked loop (CP‐PLL) with a fully digital defect‐oriented built‐in self‐test (BIST) for very‐high frequency (VHF) applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring voltage‐controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of −132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ complementary metal‐oxide‐semiconductor process.