Open AccessAnalysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise
Author(s) -
Tripathi Girish Chandra,
Rawat Meenakshi
Publication year - 2021
Publication title -
iet science, measurement and technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.418
H-Index - 49
eISSN - 1751-8830
pISSN - 1751-8822
DOI - 10.1049/smt2.12041
Subject(s) - predistortion , transceiver , amplifier , electronic engineering , computer science , field programmable gate array , noise (video) , gate array , baseband , engineering , cmos , computer hardware , artificial intelligence , image (mathematics)
The noise is an inherent part of a transceiver system, which becomes more severe on low‐cost systems. The power amplifier (PA) further enhances this noise and the signal to be propagated to the receiver. The conventional approach of digital predistortion (DPD) assumes an ideal transceiver system while extracting data for the predistortion function generation. As a result, performance limitation arises due to residual signal–noise interaction. This study presents the accuracy and implementation issues of DPD on a low‐cost transceiver having lower bit resolution in the presence of transceiver noise. Different model architectures, as well as processing algorithms, are compared in terms of numerical stability of the solution (condition number of observation matrix), efficient field‐programmable gate array (FPGA) implementation (dispersion of coefficients, in‐band model performance (normalised mean square error), and out‐of‐band model performance (adjacent channel power ratio). The simulation results are tested on FPGA and direct conversion transceiver‐based platform using PA. A long‐term evolution signal with 64 quadrature amplitude modulation is used for performance evaluation. The suitability of the various polynomial models for fixed‐point implementation and the required memory size for implementing the DPD model is further established.