Open AccessA full sequence impedance modelling and stability analysis of the virtual synchronous generator with inner loops
Author(s) -
Peng Yang,
Wang Yue,
Liu Yonghui,
Yu Peng,
Shu Sirui,
Lei Wanjun
Publication year - 2021
Publication title -
iet renewable power generation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.005
H-Index - 76
eISSN - 1752-1424
pISSN - 1752-1416
DOI - 10.1049/rpg2.12034
Subject(s) - inner loop , control theory (sociology) , electrical impedance , oscillation (cell signaling) , resistor , stability (learning theory) , generator (circuit theory) , loop (graph theory) , inertia , instability , computer science , correctness , voltage , physics , engineering , mathematics , power (physics) , mechanics , controller (irrigation) , control (management) , algorithm , electrical engineering , artificial intelligence , quantum mechanics , machine learning , genetics , biology , classical mechanics , agronomy , combinatorics
Virtual synchronous generator (VSG) has been widely studied owing to its inertia support to the grid. However, the stability of VSG is not analysed accurately for actual applications in previous studies that overlook voltage and current inner loops of VSG. Since inner loops are essential to control output voltage and current accurately in practical engineering, this study focuses on stability analysis of the interconnection system of VSG and the grid by sequence impedance modelling of VSG with inner loops. The complete sequence impedance model for VSG with inner loops is built and compared with that of the VSG‐ignoring inner loops, and then the stability is analysed based on that. It shows that inner loops bring the risk of instability and oscillation for VSG, which was not predicted in previous studies. Then, the influence of each parameter of inner loops on the impedance and oscillation is analysed, showing that the oscillation can hardly be eliminated by tuning the parameters of inner loops. Therefore, corresponding virtual resistor with proper value is studied and adopted in VSG with inner loops to avoid oscillation. Finally, the correctness of theoretical analysis and the effectiveness of the adopted virtual resistance are verified by the hardware‐in‐the‐loop experiments.