Open AccessThe switching decomposition pulse width modulation with reduced common mode voltage for reduced switch counts neutral point clamped inverter
Author(s) -
Jing Mengmeng,
Du Chunshui,
Xing Xiangyang,
Chen Zhiyuan,
Wen Chuangping
Publication year - 2022
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/pel2.12412
Subject(s) - inverter , pulse width modulation , control theory (sociology) , voltage , null vector , dwell time , computer science , duty cycle , correctness , modulation (music) , point (geometry) , switching time , topology (electrical circuits) , mathematics , engineering , algorithm , physics , electrical engineering , control (management) , medicine , clinical psychology , geometry , artificial intelligence , acoustics
Compared with a conventional three‐levelconverter, a reduced switch counts three‐level neutral point clamped (RSC‐3LNPC) inverter uses only 10 switching devices to achieve three‐leveloutput at a lower cost. However, in the RSC‐3LNPC inverter, the common modevoltage (CMV) reduction and neutral point voltage (NPV) balance are mutuallycoupled, and the buck switching module eliminates medium vectors, making conventional modulation methods no longer applicable. To address this problem, this paperdevelops a generation mechanism of the voltage and switching vectors for RSC‐3LNPC inverter and proposes a switching decomposition pulse width modulation (SDPWM) scheme. First, a virtual medium vector with two large vectors having the samedwell time is introduced. Then, the small and zero vectors with low CMV, along with the large and virtual medium vectors, are adopted, and by adjusting their dwell time, the NPV is balanced while reducing CMV. In addition, to reduce computational burden, the switching vector isdecomposed into a buck switching vector and a two‐level switching vector. Both switching vector sequences with transformed duty cycles are carefully designed to achieve only three switching transactions per switching period. Finally, validation and correctness of the proposed SDPWM scheme for RSC‐3LNPC inverterare verified by simulation and experiments.