Review of the designs in low inductance SiC half‐bridge packaging

Silicon carbide (SiC) device has become the primary choice for high‐efficiency power electronic equipment due to its excellent performance. However, its higher switching frequency and faster switching speed have also incurred new challenges, such as low parasitic inductance packaging. Despite a significant amount of literature to overview the low parasitic inductance packages, most of them focus on total parasitic inductance from different packaging technology. Here, from the viewpoint of partial inductance which includes gate loop, power loop and common source, the designs for different inductances are surveyed. The power loop is further discussed from power terminals, bonding wires and direct bonded copper (DBC) conductor traces. The effects and sources of these inductances are analyzed. Furthermore, the typical design solutions to reduce the inductances are summarized. Finally, the challenges of SiC packages are presented.