Open AccessAn improved asymmetrical multi‐level inverter topology with boosted output voltage and reduced components count
Author(s) -
Arif M Saad Bin,
Mustafa Uvais,
Siddique Marif Daula,
Ahmad Shahbaz,
Iqbal Atif,
Ashique Ratil Hasnat,
Ayob Shahrin bin
Publication year - 2021
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/pel2.12119
Subject(s) - topology (electrical circuits) , boosting (machine learning) , capacitor , network topology , voltage , computer science , inverter , modularity (biology) , electronic engineering , control theory (sociology) , engineering , electrical engineering , control (management) , computer network , artificial intelligence , biology , genetics
This paper presents an improved Multi‐level Inverter topology utilizing the concept of boosting‐capacitor and two DC sources with reduced switches count for generating 17‐level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H‐Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce ‘n’ level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are verified. Nearest level control is used as the modulation technique.