Open AccessEffect of ITCs on gate stacked JL‐TFET based on work‐function engineering
Author(s) -
Bhardwaj Eshaan,
Nigam Kaushal,
Choubey Shubham,
Chaturvedi Savitesh
Publication year - 2019
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2019.0252
Subject(s) - transconductance , work function , optoelectronics , materials science , figure of merit , electric field , linearity , intermodulation , field effect transistor , logic gate , transistor , electrical engineering , silicon on insulator , tunnel field effect transistor , silicon , physics , cmos , amplifier , nanotechnology , engineering , voltage , layer (electronics) , quantum mechanics
A stacked double gate junctionless tunnel field‐effect transistor (JL‐TFET) has been proposed and examined the effects of interface trap charges (ITCs) by introducing both acceptor and donor charges at the semiconductor/insulator interface. The structure uses two isolated gates (polarity gate and control gate) over an n‐type‐doped silicon substrate to function as a TFET. The effect of ITCs has been analysed in terms of DC and analogue/radio‐frequency performance using parameters such as transfer characteristics, electric field, electric potential, transconductance ( g m ) for both conventional and gate stacked JL‐TFET. Additionally, they have also analysed metrics used to measure the device linearity performance and intermodulation distortion such as higher‐order transconductance coefficients ( g m2 , g m3 ) and figure of merit. All the simulations have been performed with the help of an Atlas device simulator.