Open AccessApproach for fabricating JLT using chemically deposited cadmium sulphide and titanium dioxide
Author(s) -
Patil Ganesh C.,
Kristaparapu Vijayasri,
Ingle Suyog T.,
Majumder Sutripto,
Sankapal Babasaheb R.
Publication year - 2019
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2019.0018
Subject(s) - crystallinity , titanium dioxide , materials science , cadmium , titanium , transistor , sputtering , threshold voltage , nanotechnology , optoelectronics , chemical engineering , voltage , thin film , metallurgy , electrical engineering , composite material , engineering
Cadmium sulphide and titanium dioxide‐based junctionless transistor (JLT) has been demonstrated by using simple and low‐cost chemical bath deposition method. The morphological and structural study has been performed to speculate the crystallinity and the topography of individual layers of the proposed device. The optimised sputtering conditions lead to the formation of source and drain electrical contacts of the device. The fabricated device successfully functionalised as a p‐channel JLT. At the source‐to‐drain voltage of −50 V, the ON‐state drive current and OFF‐state leakage current of the fabricated JLT are found to be −6 µA and 1.3 nA, respectively.