Open AccessSymmetric dual gate insulator‐based FinFET module and design window for reliable circuits
Author(s) -
Yadav Nandakishor,
Shah Ambika Prasad,
Beohar Ankur,
Vishvakarma Santosh Kumar
Publication year - 2019
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2018.5210
Subject(s) - materials science , insulator (electricity) , optoelectronics , logic gate , leakage (economics) , gate oxide , electronic circuit , trapping , process window , mosfet , high κ dielectric , threshold voltage , voltage , and gate , electrical engineering , engineering , transistor , dielectric , ecology , biology , economics , macroeconomics , lithography
High‐k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short‐channel effects in scaled devices. The work presents a high‐performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low‐k and outer high‐k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high‐k spacer width of the SCT tolerant design. SCT analysis is presented in different high‐k spacer materials and back‐gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.